L1 Cache & L2 Cache

[Big Booger]

Ok,
So I know the difference between the two.

L1 (level 1) cache - L1 cache stores information for use by the processor. L1 cache is extremely quick but also expensive. Most processors have an L1 cache divided into space for data and space for instructions.

L2 (level 2) cache - L2 cache is the next step down from L1 cache. Most processors today have L2 cache, which increases cache performance. Most desktop processors have an L2 Cache of about 256KB, but some high-end processors can have as much as 2MB.


Now my question is this, why don't chip makers forego the L2 cache and invest more money in say 128-2Mb of L1 cache?

Obviously price is an issue.. but wouldn't L1 cache speed up the transfer and processing of data?

I am also curious about the methodology of data transfer between the two.. I mean does info first get loaded into L2, then transfered to L1 and then onto the CPU?

Any clarification about this would be helpful.
Thanks

[zipp51]

BB from what I have read the L1 cache on chip is a lower latency which is faster for calculations.The L2 is of higher latency and is used for calculations which are too big to all fit on the L1.So the L2 feeds the L1.And your right about the price issue because naturally the L1 is more expensive.Interesting question about why not just a large L1 w/o L2.

[Tinker]

My understanding if this issue is, the CPU uses L1 to talk directly to. Then L1 passes the information to L2 which passes it to the FSB and then on to memory or the AGP. L1 is indeed faster than L2 which as we all know makes it cost more. Since L1 is faster than L2 it is also faster than the FSB which means it would have to be throttled down to be put on the FSB.

P4 Cache Link... (http://sysopt.earthweb.com/articles/p4/index3.html)

Source: SysOpt.com

:D

[Big Booger]

Thanks gents. That sums it up nicely.

Tinker's article really gave focus to it with the diagrams and explanation:


The P4 data cache architecture basically remains the same as earlier Intel designs, except that its 8 KB storage limit is twice as small as the P3's 16KB specification. The inclusive nature of the Intel cache scheme doesn't require the use of a large L1 cache. Using the inclusive design approach, all data buffered by the data cache is also being buffered by the on-die L2 cache. By adding more space to the L1, there would be absolutely no reduction in the miss rate of the L2 cache. The small amount of data requests that are moved to system memory are directly governed only by the L2 cache controller, and the data present would be the same regardless of the L1 cache size.

The Level 2 cache will be 256KB in size and operate at the same speed as the CPU core global clock. As with the P3, the Willamette core will also use a 256-bit connection to the L2 region. The Willamette also has the ability to transfer cache data with every clock cycle, unlike the P3's limit of cache operations with only alternating CPU cycles. This new cache access scheme allows for 48 Gigabytes per second throughput, which is twice as much as the P3's 24Gb/s mark. Multimedia and other throughput intensive applications will directly benefit from this increased level of performance.

where they compare teh process between PIII and PIV

Interesting. I would have thought that with faster FSB speeds, the L2 cache would eventually disappear..
and L1 would take over. But I guess not.
:D